The present invention relates to a weighted mean calculation circuit for calculating a mean value by multiplying a plurality of signal voltages by weighting coefficients.
Weighted mean calculations have widely been utilized for an image process in which spatial filtering is carried out on the basis of signals from an image input device, and for a transversal filter that carries out filtering with respect to time-series data for sampling serial data at a fixed interval. Normally, there are many cases where calculations are carried out after analog signals that are sampled with respect to space or time are converted to digital signals by an A/D converter. However, as the number of signals for a calculation input is increased, such a problem arises, in which power consumption and the occupation area in a chip are increased in digital processing.
To the contrary, such a type has been proposed, in which a calculation system is employed with analog values for the purpose of a decrease in power consumption and the occupation area in the chip. FIG. 10 is an exemplary view showing a transversal filter by analog calculations. Inputted analog signals are one by one transferred as time-series analog data by a delay circuit after they are sampled, and respective sampled analog signals are multiplied by a weighting coefficient, wherein the calculated results of output are added together to obtain weighted mean outputs. By varying the coefficient, various filtering can be carried out. Also, normally, a sample hold circuit is used as the delay circuit.
Normally, a calculation circuit having such a type as shown in FIG. 11 is used as a circuit for calculating such weighted mean values. The calculation circuit shown in FIG. 11 includes a operational amplifier in which a non-inverting input terminal is grounded and a switch SW0 and capacitor CO are provided between the non-inverting input terminal and an output terminal; n capacitors C1 through Cn that are connected to the inverting input terminal; and toggle switches SW1 through SWn that are connected to either voltage of signal inputs V1 through Vn secured at the other ends of the respective capacitors or the ground.
In this construction, since the inverting input terminal of the operational amplifier is made into the ground potential in the form of hypothetical grounding if the switch SW0 is turned on and the switches SW1 through SWn are connected to the ground side, the electric charges of all capacitors become zero. Next, if the switch SW0 is turned off and switches SW1 through SWn are connected to the input signal side, the output voltage Vout is obtained by using charge conservation, and becomes as shown in the following expression:
Vout=xe2x88x92(C1*V1+C2*V2+ . . . +Cn*Vn)/C0xe2x80x83xe2x80x83(1)
Herein, if C0 is made into a sum of C1 through Cn as in the expression (2), a normalized weighted mean can be obtained in the form of an inverting output.
C0=C1+C2+ . . . +Cnxe2x80x83xe2x80x83(2)
Further, in FIG. 11, the reference voltage applied to the non-inverting input terminal and switches SW1 through SWn are made into the ground. However, a level shift may be performed by setting the reference voltage to an adequate voltage value, in order that output signal range can be effectively determined.
As an example in which such a transversal filter is used, there is an example in which the transversal filter is applied to a matched filter circuit used in a spectrum diffusion communications system for mobile communications and wireless LAN, etc., which are described in Japanese Unexamined Patent Publication Nos. 1997-46231 and 1997-83483, etc. The circuit basically employs the construction shown in FIG. 11. However, the publications describe that the power consumption of the circuit can be decreased by employing an inverting amplifier of a single end input type, which includes a series of odd number of inverters, instead of the operational amplifier.
Although it has been normal until now that calculations to obtain weighted mean values are carried out by using an inverting amplifier circuit as shown in FIG. 11, the results of the calculations become inverted outputs in the circuit. Therefore, it was necessary to add a stage of an inverting amplifier in order to directly compare the results with the original input signals. Also, in a case of digital signal processing, the weighting may be simply altered by using software. However, since it is necessary to change the capacitance of C0 to alter the capacitance of the capacitors C1 through Cn in the construction shown in FIG. 11, another problem arises, which makes the circuit complicated if such a system in which the weighting is changed by controlling it from the outside is used. In addition, further lower power consumption and a smaller occupation area are desired in order to effectively utilize the advantages of analog calculations.
It is therefore an object of the invention to provide a weighted mean calculation circuit in which output signals are not caused to have any offset with respect to input signals, and it is another object of the invention to provide a weighted mean calculation circuit that enables lower power consumption and a smaller occupation area than any of prior arts.
The invention employs the following means in order to solve the above-described objects. That is, a weighted mean calculation circuit according to the invention includes an inverting amplifier; a plurality of capacitors in which the first terminal is connected to an input terminal of inverting amplifier; switching means for feedback, which is provided between the input and output of the above-described inverting amplifier; switching means that connects the second terminals of the above-described plurality of capacitors to input signals; and switching means that connects the second terminal of the above-described plurality of capacitors to the output of the inverting amplifier.
The weighted mean calculation circuit constructed as described above operates in the embodiment including an input operation mode in which the above-described switching means for feedback is made continuous (on or closed), and a plurality of input signal voltages are applied to the second terminal of the above-described plurality of capacitors, and an output operation mode in which the above-described switching means for feedback is made non-continuous (off or opened), and simultaneously at least two or more capacitors among the above-described plurality of capacitors, in which the input signal voltages are stored, are connected to the output terminal of the above-described inverting amplifier, and in which weighted mean values being the mean values of the results obtained by multiplying a plurality of signal voltage values by weighting coefficients are outputted.
By employing such a system, differentials (Vinxe2x88x92Vth) between the input signal (Vin) and threshold voltage (Vth) of the inverting amplifier are stored in the respective capacitors when operating to input a signal (in the input operation mode), and since the signal charge stored in the respective capacitors are proportionate to the capacitance values and all capacitors are connected in parallel when operating to output the signal (in the output operation mode), the total sum of the signal charges are shared by the capacitors connected between the input and output of the inverting amplifier, wherein a weighted mean value is outputted. Also, since the same capacitance is used while the threshold voltage of the inverting amplifier is as the reference in the both of inputting and outputting operation, the output signals do not have any offset voltage, and simultaneously the output signals are caused to become normal outputs.
Also, since, in a prior art weighted mean calculation circuit, input capacitance to which an input signal voltage is applied was different from the feedback capacitance to obtain an output, it was necessary to adjust both the input capacitance value and feedback capacitance value with respect to alternation of the weighting. However, since the same capacitance is used for the input capacitance and feedback capacitance in the system according to the invention, it is sufficient to change the weighting only in the input capacitance value, and a circuit configuration that varies the weighting by controlling it from the outside by using software can be easily constructed. In addition, since no excessive feedback capacitance is provided, not only the layout area thereof can be reduced equivalent thereto, but also the bias current value of an inverting amplifier to charge and discharge the capacitance can be decreased, whereby the power consumption and the occupation area can be further decreased than in any of the prior art weighted mean calculation circuits.
In the present invention, it is preferable that the above-described inverting amplifier is a CMOS inverting amplifier including a first MOS transistor of a source-grounding type, a second MOS transistor of the same polarity, which is cascode-connected thereto, and a load type third MOS transistor of the polarity opposite thereto. If such an inverting amplifier composed of the first MOS transistor and second MOS transistor, which are cascode-connected, is used, the gain can be increased using only one stage of the inverting amplifier to enable a decrease in power consumption and simultaneously increase the operating rate.
In the present invention, it is preferable that the above-described plurality of input signal voltages are applied in parallel by a plurality of terminals, a switch connected to the corresponding input signal terminal and a switch connected to the output terminal of the above-described inverting amplifier are provided at the second terminals of all the capacitors, whereby it is possible to output a weighted mean calculation value after input signals are simultaneously applied to respective capacitors with respect to a plurality of signals applied in parallel.
Also, in the invention, it is preferable that the above-described plurality of input signal voltages are applied from one terminal in series, switches connected to a common node are provided at the second terminal of all the capacitors, and simultaneously the above-described common node has a switch connected to the input signal terminal and a switch connected to the output terminal of the above-described inverting amplifier. With such a construction, it is possible to output weighted mean calculation values with respect to the input signals applied one after another in a time series.
In the invention, it is preferable that an element that constitutes one capacitor with respect to one input signal among a plurality of capacitors corresponding to the input signal voltages is further composed of a plurality of capacitors, and simultaneously, connection of a plurality of capacitors corresponding to the input signal is varied by a control signal from a control section, whereby it is possible to vary the weighting. Therefore, since applied control signals can be varied from the outside, alternation of coefficients can be carried out by modifying the software, wherein the invention can be used for various uses.
Also, in a case where components of capacitance inputted with respect to one signal voltage is composed of a plurality of capacitors, it is preferable that the ratio of capacitance values are made into 2 to the power of J (J is the integral number) like 1:2:4:8, whereby it is possible to maximize the range of variation of the weighting with a slight number of control signals.
Further, it is preferable that either one of the voltage values which are obtained by equally dividing two voltage values, which become the reference, into xe2x80x9cnxe2x80x9d pieces is selectively inputted as a plurality of input signal voltage values. Input voltages which are in such a relationship are selected and combined, and provided to the respective capacitors, whereby it is possible to constitute a digital-analog converter (D/A converter).
In addition, it is preferable that a plurality of input signal voltages are provided with either one of the two voltages that become the reference is selectively provided, and the ratio of a plurality of capacitors is in a relationship where it is made so as to have 2 to the power of J (J is the integral number) like 1:2:4:8, whereby it is possible to constitute a digital-analog converter (D/A converter) that can obtain an optional output with minimized control.
As a further detailed composition of the invention, the above-described inverting amplifier is made into a CMOS inverting amplifier, whose stage of amplifier is singular, that includes a source-grounding type first MOS transistor, a second MOS transistor of the same polarity, which is cascode-connected thereto, and third MOS transistor, which is used as a load, having the polarity opposite to that of the above-described first MOS transistor, the above-described capacitance is constructed as a capacitance element formed on the MOS process, and the switching means are also respectively-constructed by using a MOS transistor.